This webpage serves as my personal showcase of my work done while with the BRICCS Group at Virginia Tech. This will include links to any publications, journal entries, and blog posts.

Background

My name is Aaryan Dhawan and I’m a Computer Engineer, specializing in RTL design and computer architecture. I’m based in the Northern Virginia area and attended Virginia Tech for my Bachelors of Science, Computering Engineering, majoring in chip-scale integration (BSCPE-CPI). Still at VT, I’m now pursuing a Master of Engineering in CPE on the VLSI and Design Automation track. I am a member of the Brain Inspired Computing, Communications, and Security (BRICCS) Group, based at the Virginia Tech Institute for Advanced Computing in Northern Virginia, where I’ve been researching novel Spiking Neural Network designs and their implementations on FPGAs.

Portfolio [Coming Soon]

The Portfolio section will contain selected projects completed during my academic career at VT. These projects are the ones that I found the most memorable, challenging, or a mix of both. These will range from RTL design projects, VLSI layout designs, and some semiconductor based work.

Blog

The Blog section will mostly contain supplementary material for my research work with the BRICCS Group, revolving around Spiking Neural Networks and their implementations on FPGAs. This will include code snippets, explanations, and any other relevant information that may be useful to others in the field.